Basic Verilog learning

Verilog is a hardware description language and with simulation tools you can describe a harware and simulate it. here I want to introduce it in a basic level which is useful for sophomores who are studying computer or electrical engineering. This tutorial is useful for Digital Logic Design course.

As you know in the DLD course all things will be build by transistors. So we start simulation in the switch level (transistor level). You can use two type of transistors NMOS and PMOS.PMOS always connects to the supply1 (means it connects to the voltage which is larger than zero) and NMOS vice versa (means it always connects to the Ground = 0 voltage or as Verilog calls is supply0).

Hardware that we use has a delay to reach a stable situation. Verilog in the transistor level models this delay with three numbers:
1) delay to change the situation of the transistor from any other situation to 1
2) delay to change the situation of the transistor from any other situation to 0
3) delay to change the situation of the transistor from any other situation to Z
note : Z means a wire which is not connected to the voltage or ground

   So we can get an instance from NMOS or PMOS transistor in below pattern:

         nmos #(to 1 delay, to 0 delay, to Z delay)name of the transistor(output, input, control)
         pmos #(to 1 delay, to 0 delay, to Z delay)name of the transistor(output, input, control)
input also is called Source.

   As you can see, you can select a name for your each transistor, as I mentioned before you should connect input of PMOS to voltage and NMOS to ground. Each transistor is controlled by a “control wire” and it controls transistors in below manner:
When control wire is 1 ,NMOS connects input to the output and when it’s 0 NMOS don’t connect.
When control wire is 1, PMOS don’t connect input to the output and when it’s 0 PMOS connect.

To connect transistors to each other you should wire (Verilog calls them wire too).

In Verilog we define each component ( a nand gate, comparator etc ) in a block called module. Each module starts with keyword “module” and will be complete with keyword “endmodule”. You can define inputs and outputs for your component. For example in below code you can see implementation of a NAND gate ( delays are at pleasure ).

Module myNANDgate( input A,B,output W);
     supply1 Vdd;                       //to be easy we’ll call supply1 Vdd (supply 1 is voltage)
     supply0 Gnd;              //to be easy we’ll call supply0 Gnd (supply0 is ground or zero voltage)
     wire i;                                              //to connect transistor T1 to T2 we’ll use wire
     pmos #(5,6,7)T1(i,vdd,A);
     pmos #(5,6,7)T2(w,i,B);
     nmos #(3,4,5)T3(w,Gnd,B);
     nmos #(3,4,5)T4(w,Gnd,A);
endmodule

To test your component you can build a test bench, for that you should write another module and get an instance from your component, and then you can give inputs and watch outputs. For that use “ initial begin ”syntax, in this block of code commands will be done sequential and after each change you determine a time to allow your component reach its stable situation. See below example:

Module testBech();
     wire a,b,c;
     myNANDgate nandInstance (a,b,c);   //instantiation
     initial
     begin
          a=1;
          b=1;
          #30;                                                              //time to reach stable situation
          b=0;                                                             //changing input
          #30;
     end
endmodule

To compile and simulate t your code use below guide:

Note : this instruction is belongs to:
ModelSim ALTERA WEB EDITION 6.3g_p1
Revision: 2008.08

1) Start ModelSim

2) Click on file menu New->Project…

3) In the “Create Project” pop-up window write a name, select a directory and click OK

4) In the “Add items to the Project” click on the “Create New File”, select a name for your file and from “Add file as type” select Verlog.

5) Add as many as files that you need (in the above example you need two files one for NAND implementation and other for test bench.

6) After writing your code from Compile menu select Compile all. You should see a green sign in front of your file name in the Workspace window/Project tab.

7) From simulate menu select “start simulation”

8) In the Start Simulation window below “Name” find “work” and in it find your test bench. Click on it and select OK.

9) In the Instance window/sim tab right click on your test bench name, from menu select “Add” then “Add to Wave”.

10) Go to “Simulate/ Run/ Run All”.

11) You should see your signals!

12) Go to “Simulate/ End Simulation” to end your simulation.

Be aware to save and compile after any change in your files.

To be continuing…

Basic Verilog learning

مطالب مشابه :

Basic Verilog learning

انیمه ی افسانه ی یوگی اوه

معرفی انیمه های پاییزی - معرفی انیمه ی Akatsuki no Yano

…::|| دانلود فیلم As Good as It Gets محصول سال ۱۹۹۷ امریکا ||::…

دانلود انیمه black rock shooter

دانلود انیمه کوباتو با زیرنویس فارسی

دانلود انیمه لوپس گاروس